My CPU Design

Submitted by Andrew Wasson on Thu, 01/12/2012 - 6:39pm

My CPU is a 4-bit RISC (reduced instruction set computer) design and has a maximum of 16 instructions. I chose a 4-bit CPU because it will be easier to troubleshoot than one with a wider datapath and the lessons I learn building this one can be built upon as I move to more complicated larger processors.

Old School Technology
I'm going old school with this build. It's going to be a slow running processor and the design will be limited to my imagination and skills but it's inspired by the processor detailed in the CHUMP Paper at Dave Feinberg's Projects webpage.

I'm using 7400 series TTL chips to build it. I've got a small RAM chip for the program instructions. I'm going to add a front panel with toggle switches so that the CPU can be switched into 'program' mode and the program memory chip can be loaded with the instructions that make up a program. There is another RAM chip for program data so that the programs can store or manipulate data while running. The control portion of the CPU that interprets the instructions and determines what actions take place will be mainly handled by a single 8-bit EPROM chip (Erasable Programmable Read Only Memory). The clock will be handled by a 555 timer chip. I think I can pull it off with 15 chips including two RAM chips and one EPROM but I may add a tristate buffer between the program memory and the control logic to simplify switching from normal to program mode.

CPU Topography
The CPU is made up of several systems which are connected by control circuitry. They are simple circuits that combined form to make a more complicated circuit. Below are descriptions the parts that make up this CPU.

  • The Clock Circuit is about as simple as it can get. It's just a simple timer circuit that generates a train of pulses. The output of the clock generator is connected to the inputs of the other circuits so that they act in unison as the instructions are acted on. I thought I could use a simple 555 ciscuit in astable mode to generate the pulse train but it seems to be unstable as the frequency gets about 10Hz - 15Hz so I'll have to figure out a better circuit when I decide to speed things up.
     
  • The Program Counter is the next circuit in line. I am using a pair of 74LS161 chips cascaded as an 8 bit counter so that they count in hexadecimal from 0 to 255. The 74LS161 chip counts continuously as long as it receives a pulse on its clock input and can be reset to zero or a new number can be set into the clock register. I am using this ability to apply a new number to the counting register for my JMP (Jump) instruction.
     
  • Instruction Memory consists of a single 8-bit static RAM chip. Pretty much any memory chip will do the job. I'm using a common 6116 chip. The program instructions are entered into the RAM 8 bits at a time (4-bit operator, 4-bit operand) and when the CPU is in run mode, the program counter indexes the address bus sequentially and the instructions are read on the Instruction Bus.
     
  • Program Memory consists of 16 multipurpose areas in a second RAM chip for storing and retirieving data for use in programs.
     
  • For Arithmetic Logic (ALU), I'm using a 74LS181 chip. This greatly simplifies the CPU, reduces the chip count and should make the CPU easier to troubleshoot once I get it going.
     
  • The Control Logic is generally the most tricky part but in this build it is simplified because in this case the instructions are made up of a 4-bit OpCode paired with a 4-bit Operand. Each OpCode is directed to a Primary Control Bus whch addresses the control ROM and each Operand is directed to an internal data bus. The control ROM outputs to a Secondary Control Bus that all of the sub systems are connected to. A great deal of the Control Logic is programmmed into the control ROM which in turn reduces the circuits complexity and part count. The control ROM can be thought of as a 4 in - 8 out programable multiplexor.    

8-Bit Address Bus
Most of the 4-bit processors I've seen in my research have 4-bit address busses which limit them to programs with a maximum of 16 steps. Since I'm planning to program my CPU to do something more than flash a few LED's I figured I would need at least an 8-bit address bus. This is a relatively easy thing to do and I've added some extra circuitry so that I can program it to jump to an 8-bit address space with two 4-bit commands. First you set the upper 4-bits and then you enter the command for the lower 4-bits. If the upper 4-bits have been set then the full 8-bit address is set on the program counter. If only the lower 4-bits have been set then the program counter will go to the lower 4-bit address within the current upper 4-bit address space.  

I've got some other ideas about how to expand the instruction set and memory but first I have to see if I can get this thing to actually run some code.  My next steps are to add the front panel, wire up the permanent clock circuit and then I have to wire the dreaded control circuitry and troubleshoot it.

EDIT (Jan 21, 2012): Since I decided to redesign the CPU board layout and refine some of the wiring I have a bunch more work to do before I can get to the control circuitry. I've installed the permanent clock circuit on the board that holds the PC and JUMP logic and I'm about half way through the new RAM board. I still have to finish up the front panel display board and then I might redo the layout for the ALU, Multiplexor and Accumulator so I can clean up the wiring and add decoupling caps to all of the chips.

EDIT (Feb 8, 2012): I'm getting busy with Eagle (light) software and documenting my schematics. I'm a rank amature with the software and haven't figured out how to properly terminate my connections but this is much better than scribbles on paper. Check them out on the Schematics page.

Check back regularly, I'm updating this page as the project evolves.

7 comments

by ytq7g on Sat, 05/19/2012 - 5:25am

I am really impressed with your writing skills and also with the layout on your blog. Is this a paid theme or did you customize it yourself? Anyway keep up the nice quality writing, it is rare to see a great blog like this one today..
wesdf

by Andrew Wasson on Sun, 05/20/2012 - 9:52pm

Thanks for the complements. I'm just getting back into the project and working out the controi circuitry so there will be some updates soon.

The blog runs on Drupal and the theme is a free one that is based on a Wordpress theme called Tarski. I thought it was a nice theme that didn't overcomplicate things. Here are some links:

by jerry uhler on Sun, 07/08/2012 - 1:36pm

for the most simple
lda (address)
sto (address)
jnz (adress) jump if acc not zero
its a bit tricky to get other needed funtion with these 3 insturtions but it can be done
basicly self modifling code example of not is simple
have an table of nots in memory
address content
????.????.0001 1110
????.????.0010 1101
etc....total of 16 addresses
256 addresses for and
16 addresses for shift left and 16 for right shift
16 addresses for +1 and 16 addresses for dec -1
that it for tables total of 336 nibbles

jerryuhler@gmail.com

by Andrew Wasson on Sun, 07/08/2012 - 5:40pm

Hi Jerry,
Thanks for the comments... I've been busy with other things for the past couple of months but was just going over the CPU this afternoon, looking at next steps. Did you see the instruction set that I'm proposing (http://www.ttlcpu.com/articles/instruction-set)? My plan is to complete the 4-bit processor with that instruction set and then build a Mark II version with 5-bit instructions so I can have 32 instructions rather than just 16. Eventually I'll move on to an 8-bit processor but 4-bit is easier to manage  for now.

Cheers,
Andrew

by Dave Feinberg on Tue, 08/28/2012 - 8:12am

Very glad to see you're building on my CHUMP design. I definitely agree with your plan for 8-bit addressing.

by Andrew Wasson on Tue, 08/28/2012 - 12:35pm

Thanks Dave,

I really like the program that you put together and I think when the student learns what's going on at such a low level to the point that they know what's happening at each pulse from the clock and how to configure gates and micro-instructions to achieve their goals, they can only become better IT professionals, regardless of what direction they take. When I was in high school, I learned about the 1802 chip which was a RISC chip and I often refer to those concepts when I'm writing code or designing software of some sort.

Cheers,
Andrew

by Myk Dormer on Sun, 06/08/2014 - 4:34pm

Fascinated to read the details of your processor design. Simple TTL CPU designs are entrancing things to work on. (I'm a fellow "sufferer", currently building a 16bit (or is it 24bit?) design. Details on Facebook: https://www.facebook.com/groups/553432921406179/ )

I especially like your "JCC" instruction. Removes the need for a "clear carry" instruction (although non-conditional jumps must be a bit awkward)

Myk

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