I'm starting to make some progress with Eagle (light) and I'll be adding schematic diagrams of all of the circuits that make up my CPU.
I just finished doing the 3rd Eagle layout of the program counter and this one actually makes sense to look at. The first two were a mess of wires intersecting and crossing over each other so that it was hard to see what was connected and what wasn't. Hopefully anyone looking at this diagram can follow along and get what I'm aiming for.
- A0 through A7 connect to the 8-bit address bus that the instruction RAM is connected to.
- CLK and CLK1 get connected to the clock signal.
- A-0 to A-3 and B-0 to B-3 are on the same 4-bit bus that connects to the instruction opperand through the control circuitry so that new addresses can be loaded into the program counter through the JUMP instruction. When testing they should have pull-up/down resistors or switches holding them at hi/low.
- FLAG and SET are active low and used to set the upper 4 bits of the address register for an 8 bit JUMP.
- FLAG should have a 5K pull-up resistor to V+ attached but I missed that on the schematic. I'll ammend it and upload it later.
- Taking pin 1 on the 74LS174 low will reset the upper 4 bit register.
- Taking pin 1 on both 74LS161's low will reset the counter to zero.
The clock circuit is a simple 555 circuit with an adjustable rate via a potentiometer. It works for now but I have to refine my component values to make it work at speeds higher than about 10Hz. I suspect that the duty cycle isn't well balanced related to the frequency. I'll have to scope it to see what's really going on but I think the length of the pulse is too short as the clock speeds up because my counters should be able to work at speed but they start stalling when I get going past 10Hz which is pretty slow.